Chip design verifying and chip testing apparatus and method

ABSTRACT

A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the storing means and the chip, and having a data applying means for applying the I/O file and/or the test vector outputted from the storing means and a data storing means for storing data outputted from the chip; and a computer including a CPU for performing and controlling the application program.

CROSS REFERENCE

[0001] This application claims the benefit of Korean Patent ApplicationNo. 2000-30625, filed on Jun. 3, 2000 and the benefit of Korean PatentApplication No. 2000-42575, filed on Jul. 25, 2000, under 35 U.S.C. §119, the entirety of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a chip design verifying and chiptesting apparatus and method.

[0004] 2. Description of Related Art

[0005] As electronic design automation (EDA) tools, which relates to adesign automation and a design technique utilizing a hardwaredescription language (HDL), are widely used in various electronicindustrial fields, a design circumstance of an application specificintegrated circuit (ASIC) has become greatly improved. For example,compared with the existing circuits having a capacity of from tens ofthousands to hundreds of thousands of gates, recently circuits have beendesigned to have a capacity of millions of gates, and thus the ASICdesign circumstance is improved enough to embody a system on a chip(SOC).

[0006] To embody such a circuit having a large-sized capacity on oneASIC element becomes possible due to a submicronized semiconductorprocess. As a semiconductor process becomes more submicronized, the ASICelement shows a tendency of a higher integration and a higher speed. Inembodying a large-sized and complicated circuit on the ASIC element, oneof the most troublesome cores relates to a verification of a properoperation of the designed circuit during a simulation and a systemoperation.

[0007] Since a circuit designer can estimate what the output results arefor given inputs, a simulation is just a procedure confirming such asimple function without covering corner cases. When the designed circuitis mounted on a system board, the circuit on the system always does notgenerate inputs of the same form as inputs that are used to run asimulation for the function of the designed circuit. This is one of thegreatest causes of the ASIC failure occurred when a simulation issufficiently not performed.

[0008] As a circuit to be designed becomes complicated, and anintellectual property (IP) blocks to be recycled becomes increased innumber, it becomes more difficult to make out a pattern of a simulationthat can perfectly perform an operation of a chip on a system.Particularly, in case of a circuit having millions of gates, it requiresmuch time to perform a simulation that is operated by a command languageof a microprocessor.

[0009] In order to overcome the problems occurred during a simulation byusing a hardware method other than a software method, a fieldprogrammable gate array (FPGA) that is re-programmable is widely used asa debugging means. As another solution for the problems, an ASICverifier having a more effective debugging means and based on such anFPGA has been used. The FPGA is a device that a user runs a compile byusing the user designed circuit as a compile input for the FPGA anddownloads the result bit stream file to the FPGA, so that the userdesigned circuit is formed in the FPGA in the form of a hardware. TheFPGA is generally used to effectively verify a relatively small-sizedcircuit, and thus an ASIC verifier of a high performance is required toeffectively verify a relatively large-sized circuit.

[0010] As an example of a conventional chip design verifying apparatus,a computer built-in chip design verifier is disclosed in U.S. Pat. No.6,009,256. The computer built-in chip design verifier includes a processfor processing a software model of a chip to be designed in the computerand a re-configurable hardware board for embodying a hardware model toembody a chip and verifies an operation of an embodied chip. Thecomputer built-in chip design verifier can organically be operated byconnecting a target to which the designed chip will be applied to anexternal portion of the computer. However, as described above, thecomputer built-in chip design verifier includes a hardware boardconstructed with a field programmable gate array to embody a hardwaremodel of the designed chip. Therefore, since it does not use a datacompression method for a data transmission between a main memory of anda hardware board of a computer, a performance improvement is limited. Inaddition, as a hardware configuration of a circuit becomes complicated,a large number of hardware boards should be provided. Moreover, thecomputer built-in chip design verifier verifies an operation of a chipdesigned at a chip designing step but does not provide a function fortesting an operation of the manufactured chip.

[0011] As another example of a conventional chip design verifier, acomputer stand-alone chip design verifier is disclosed in U.S. Pat. No.5,963,735. The computer stand-alone chip design verifier includes anemulator, a VLSI apparatus and a memory, outside a computer. Thehardware emulator includes a configuration circuit, a logicanalyzer/pattern generator, field programmable gate arrays, and aninterface circuit. A design circuit and an application program arearranged in the computer. In order to embody a function of a circuit tobe verified by performing a series of processing steps and a compilethrough an application program, bit stream files corresponding to eachof the field programmable gate array are produced to respectively bewritten on the field programmable gate arrays. The user can control thehardware emulator using a software environment of an applicationprogram. The computer stand-alone chip design verifier includes fieldprogrammable gate arrays in order to embody a hardware model of a designto be verified.

[0012] As a graphic-related application example, the computerstand-alone chip design verifier should include an interface circuit ora separate interface circuit for an interface between the hardwareemulator and a monitor for a screen output. In other words, sincesignals from the hardware emulator are outputted at a low speed, in caseof directly displaying the signals on the monitor, a normal screen maybe not outputted. Therefore, the interface circuit should be providedbetween the hardware emulator and the monitor to output a normal screen.

[0013] As described above, the conventional chip design verifiers have aproblem in that a suitable hardware verifying environment should beprovided additionally. That is, in case of a graphic-related design,additional graphic data buffering apparatus and a monitor to output ascreen should be provided to monitor a screen output. Moreover, eventhough the conventional chip design verifiers can verify an operation ofthe designed chip, there comes a problem that it can not test anoperation of the manufactured chip. Besides, the conventional chipdesign verifiers include standard means in themselves that can contain adesign to be verified and focus on how to offer the results of thedesign to be verified to the standard means in a desirable manner,whereas they can not provide a proper window environment for anuniversal verification regarding how to effectively verify a design tobe verified that is constructed with various functional blocks,according to each of the functional blocks, and how to effectivelyperform a debugging and to easily find errors.

SUMMARY OF THE INVENTION

[0014] It is an object of the present invention to provide a chip designverifying and chip testing apparatus that can be used both as a verifierto verify an operation of a designed chip and as a tester to test anoperation of a manufactured chip.

[0015] It is another object of the present invention to provide a chipdesign verifying and chip testing apparatus that can easily detecterrors.

[0016] In order to achieve the above object, the preferred embodimentsof the present invention provides a chip design verifying and chiptesting apparatus. A storing means stores an application programverifying an operation of a designed chip and testing a manufacturedchip having a plurality of blocks, an I/O file, and a test vector. Aninterface means controls a data transmission between the storing meansand the chip, and has a data applying means for applying the I/O fileand/or the test vector outputted from the storing means and a datastoring means for storing data outputted from the chip. A computerincludes a CPU for performing and controls the application program.

[0017] When the application program is executed, a graphic userinterface is displayed on a monitor of the computer, and a verifyingmode or a testing mode is set through the graphic user interface, andresults corresponding to the plurality of the blocks are displayed on acorresponding window.

[0018] The preferred embodiment of the present invention furtherprovides a chip design verifying and chip testing method. The methodincludes: providing a computer including a storing means, the storingmeans storing an application program for verifying a designed chip andtesting a manufactured chip having a plurality of blocks, an I/O file,and a test vector; executing the application program to display agraphic user interface on a monitor of the computer; storing alternatelydata constituting the IO file and/or the test vector stored in thestoring means in a data applying means when an operating mode is set toa verification mode to verify an operation of the designed chip throughthe graphic user interface; storing alternately data outputted from thechip in the data storing means; storing alternately data constitutingthe test vector stored in the storing means in the data applying meanswhen the an operating mode of the chip is set to a test mode to test themanufactured chip through the graphic user interface; and storing dataoutputted from the chip in the data storing means while applying dataconstituting the test vector stored in the data applying means to thechip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a more complete understanding of the present invention andthe advantages thereof, reference is now made to the followingdescriptions taken in conjunction with the accompanying drawings, inwhich like reference numerals denote like parts, and in which:

[0020]FIG. 1 is a block diagram illustrating a configuration of atypical computer system;

[0021]FIG. 2 is a block diagram illustrating a chip design verifying andchip testing apparatus according to the preferred embodiment of thepresent invention FIG. 3a shows an embodiment of a target;

[0022]FIG. 3b shows another embodiment of the target;

[0023]FIG. 4 is a block diagram illustrating an embodiment of aninterface means of the chip design verifying and chip testing apparatus;

[0024]FIG. 5 is a block diagram illustrating a controller of FIG. 4;

[0025]FIG. 6a shows an embodiment of a module for a connection betweenthe interface means and the target;

[0026]FIG. 6b shows another embodiment of a module for a connectionbetween the mainframe and the target;

[0027]FIG. 6c shows an embodiment of the connecting board that ismounted on PCI slots when the interface means is mounted on the moduleof FIG. 6B;

[0028]FIG. 6d shows an embodiment of an appearance form of the interfacemeans that is mounted on the module of FIG. 6B;

[0029]FIG. 6e shows another embodiment of the module for a connectionbetween the interface means and the target;

[0030]FIG. 6f is an embodiment of a back board of the module accordingto the preferred embodiment of the present invention;

[0031]FIGS. 7a to 7 c shows a flow chart illustrating an internaloperation of the mainframe when the chip design verifying and chiptesting program of the chip design verifying and chip testing apparatusis executed;

[0032]FIG. 8 shows an allocation of a memory region inside a mainframewhen the chip design verifying and chip testing program is executed;

[0033]FIG. 9 shows an embodiment of a GUI displayed on a monitor of FIG.1 when the chip design verifying and chip testing program is executed;

[0034]FIG. 10 is a table showing a relationship between a symbolrepresenting a logic state and a meaning of the symbol;

[0035]FIG. 11 shows a data format when an input file selected by thechip design verifying and chip testing program is compressed using asoftware program and then is transmitted;

[0036]FIG. 12 shows an embodiment of a test vector stored in a harddisk;

[0037]FIG. 13 shows input and output data of the test vector that arecompressed in the data format of FIG. 11, and a logic state of and a runof the input data of FIG. 12;

[0038]FIGS. 14a to 14 c are a flow chart illustrating a chip designverifying method by the inventive chip design verifying and chip testingapparatus;

[0039]FIGS. 15a to 15 c are flow charts illustrating an operation toverify the target using the chip design verifying and chip testingapparatus according to the preferred embodiment of the presentinvention;

[0040]FIG. 16a shows a data transmission method when a data transmissionspeed of from the interface means to the target are equal to a datatransmission speed of from the target to the interface means;

[0041]FIG. 16b shows a data transmission method when a data transmissionspeed of from the target to the interface means is faster than that offrom the interface means to the target;

[0042]FIG. 16c shows a data transmission method when a data transmissionspeed of from the target to the interface means is slower than that offrom the interface means to the target; and

[0043]FIGS. 17a and 17 b are a flow chart illustrating a chip designverifying and chip testing method according to the preferred embodimentof the present invention.

DETAILED DESCRIPTION OF PREFFERED EMBODIMENTS

[0044] Reference will now be made in detail to a preferred embodiment ofthe present invention, example of which is illustrated in theaccompanying drawings.

[0045] Returning now to FIG. 1, which shows a configuration of a typicalcomputer system, the computer system includes a monitor 1 and a computermainframe 2. The computer mainframe 2 includes a central processing unit(CPU) 10, a graphic signal processor 12, a graphic memory 14, a hostbridge 16, a main memory 18, a PCI/ISA bridge 20, a hard disk drive 22,PCI slots 24, and an ISA slot 26.

[0046] The CPU 10 executes an application program and performs afunction to control the computer system. The host bridge 16 performs aninterface function among the CPU 10, the main memory 18, the graphicsignal processor 12, the PCI/ISA bridge 20, and the PCI slots 24. Themain memory 18 stores application programs and various kinds ofinput/output data that the CPU 10 brings from the hard disk 22. Thegraphic signal processor 12 is connected with the graphic memory 14, sothat graphic-related signals transmitted from the main memory 18 arestored in the graphic memory 14. The graphic signal processor 12processes the graphic-related signals to be displayed on the monitor 1.The PCI slots 24 are connected with the PCI bus to transmit data andinclude LAN card slots, faxmodem slots, etc., for, respectively,accepting LAN interface cards, faxmodem card, etc. The PCI/ISA bridge 20performs an interface function among the host bridge 16, the main memory18, the hard disk 22, the PCI bridge 24, and the ISA slot 26. The harddisk 22 stores application programs and various kinds of data. The ISAslots 26 are connected with the ISA bus to transmit data. In FIG. 1,even though four PCI slots 24 and one ISA slot 26 are arranged, thenumber of the PCI slots 24 and the ISA slots 26 is not limited to thepresent invention.

[0047]FIG. 2 is a block diagram illustrating chip design verifying andchip testing apparatus according to the preferred embodiment of thepresent invention. As shown in FIG. 2, the chip design verifying andchip testing apparatus includes the mainframe 2 that has a chip designverifying and chip testing program 30 and an interface means 32, and atarget 34. That is, the chip design verifying and chip testing apparatusis constructed in such a way that the chip design verifying and chiptesting program 30 is stored in the hard disk 22 of the mainframe 2 ofthe computer system of FIG. 1, and the interface means 32 is accepted inthe PCI slots 24 that is connected to the PCI bus.

[0048]FIG. 3a shows an embodiment of the target. The target of FIG. 3aincludes software intellectual property (IP), a FPGA, a memory, and amicro controller unit (MCU). The software IP is embodied using thememory and the micro controller unit or a corresponding hardware IP. TheFPGA stands for a field programmable gate array and is a hardware modelfor embodying the hardware portion of the user designed chip. The memoryand the MCU are embodied using a universal chip. That is, the target 34of FIG. 3a is one which embodies the software IP, the hardware IP thatis an universal chip, the memory, the micro-controller unit, and theFPGA embodying the hardware portion non-embeddable by the universalchip.

[0049]FIG. 3b shows another embodiment of the target. The target of FIG.3b includes an audio, a video, a telecommunications, a peripherycircuit, an MCU, a read only memory (ROM), a random access memory (RAM),and a hardware IP. The target of FIG. 3b is manufactured by a customerorder. The audio, the video, the telecommunications, and the peripherycircuit are blocks corresponding to the FPGA of FIG. 3a. The ROM and theRAM are blocks corresponding to the memory of FIG. 3A. The hardware IPis a block corresponding to the software IP.

[0050] The target 34 is not limited to a certain target. As shown inFIGS. 3a and 3 b, the target 34 may be a designed chip that isdeconstructed by the universal chip and the field programmable gatearray. Or, a hardware emulator may be used as the target 34. After achip is manufactured, the target 34 may be a manufactured chip of FIG.3b.

[0051]FIG. 4 is a block diagram illustrating an embodiment of theinterface means of the chip design verifying and chip testing apparatus.The interface means 32 includes first to fifth connectors C1 to C5, amemory 40 having first and fourth memories M1 to M4, a controller 42, abus termination circuit 44, a reset circuit 46, and a switch SW. Theinterface means of FIG. 4 is one that shows a configuration of theinterface board and is inserted into the PCI slots 24 of the mainframe 2of FIG. 4 through a connecting portion 48.

[0052] The first connector C1 is connected to the memory 40 toinput/output signals and is used to expand a memory capacity by beingconnected with either a memory board thereto or a memory of aneighboring interface means 32. The connector C2 is used to connect theinterface means 32 with each other when a plurality of the interfacemeans 32 are inserted into the PCI slots 24. The third connector C3 isconnected with the target 34 via, for example, a connection cableaccording to a pin to signal mapping of an application program. Thethird connector C3 is arranged on a front surface of the mainframe 2because a front surface of the mainframe 2 is larger in space than aback surface. The fourth and fifth connectors C4 and C5 are used toconnect a standard signal inputted from an external clock generator orthe target 34, a clock signal transmitted from the interface means 32 tothe target 34, or a control signal transmitted from the interface means32 to the an external pulse generator (not shown). Preferably, thefourth connector C4 is arranged on a front surface of the mainframe 2,and the fifth connector C5 is arranged on a back surface of themainframe 2. The fourth and fifth connectors C4 and C5 are used toconnect various kinds of signals between the controller 42 of theinterface means 32 and the target 34 or between the controller 42 and anexternal measuring instrument (not shown) such as a function generator(i.e., a frequency generator). Of four memories M1 to M4 of the memory40, the two stores data received from the main memory 18 and outputs thestored data to the target 34, and the other two stores data outputtedfrom the target 34 and outputs the stored data to the main memory 18.The reset circuit 46 generates a reset signal by an operation of anexternal reset switch (not shown). The bus termination circuit 44buffers data outputted from the controller 42 to be applied to the thirdconnector C3 during a data outputting operation and buffers data appliedfrom the third connector C3 to be applied to the controller 42 during adata inputting operation. The switch SW includes a DIP switch to set anidentification number of a certain interface means 32 when a pluralityof the interface means 32 are accepted in the PCI slots 24. Thecontroller 42 controls a data transmission from the main memory 18 tothe memory 40, from the memory 40 to the target 34, from the target 34to the memory 40, and from the memory 40 to the main memory 18.

[0053]FIG. 5 is a block diagram illustrating the controller of FIG. 4.The controller 42 includes a reset processor 50, a plug and playcontroller 52, a PCL local bus interface controller 54, an addressgenerator 56, a memory controller 58, a universal register controller60, an interrupt controller 62, a trigger condition controller 64, aclock controller 66, a read-back/JTAG controller 68, a parallel/serialconverter 70, a data compression/restoration controller 72, a targetinterface controller 74, a bus termination circuit controller 76, and aglitch detector 78.

[0054] The reset processor 50 performs an initialization operation ofinternal registers of the controller 42. A reset signal is applied byone of an external reset switch, a chip design verifying and chiptesting program, and the PCI bus system, or by a normal termination ofan operation when the last frame is completely transmitted. The plug andplay controller 52 controls various kinds of PCI configuration registers(not shown) for a plug and play operation. The PCI local bus interfacecontroller 54 is connected directly with various kinds of PCI-relatedsignals and performs an interface control between the main memory 18 andthe memory 40 of the interface means 32 via the PCI bus. The addressgenerator 56 generates an address for the memory 40 of the interfacemeans 32 during a data transmission between the main memory 18 and thememory 40 of the interface means 32 or between the memory 40 of theinterface means 32 and the target 34. The memory controller 58 directlyaccesses the memory 40 of the interface means 32 according to a controlsignal of the PCI local bus interface controller 54 and the targetinterface controller 74 to perform a data transmission operation. Theuniversal register controller 60 checks various kinds of states of theinterface means 32 that may occur according to a data transmissionoperation and stores the result in the universal register therein. Theinterrupt controller 62 controls an interrupt generation to ask a datatransmission between the main memory 18 and the memory 40 of theinterface means 32. The trigger condition controller 64 is operated by ahigh sampling frequency to embody a logic analyzer. Also, by usingvarious kinds of graphic user interfaces (GUI) that is displayed on ascreen by executing a chip design verifying and chip testing program,the trigger condition controller 64 detects a location consistent with atrigger condition when the trigger condition which a user sets for acertain I/O data received/outputted through the datacompression/restoration controller 72 is received while monitoring inputand output signals of the target 34 in real time. Also, the triggercondition controller 64 can set input or output frame step number or theclock step number which a user sets through the GUI as a triggercondition. When the input or output frame step number is set as atrigger condition, a trigger operation is performed at a position wherethe input or output frame number that is counted in a process forprocessing input/output data of the data compression/restorationcontroller 72 is consistent with the input or output frame step numberset as a trigger condition. In the same way, when the clock step numberis set as a trigger condition, a trigger operation is performed at aposition where, of clock signals generated from the clock controller 66,a counting result of a clock signal set as a trigger condition isconsist with the clock step number set as a trigger condition. Thetrigger condition is applied individually or sequentially by a priority.When a trigger location is detected using the method described above,the trigger condition controller 64 stores informations regarding astart address, a memory region of the start address, an end address, anda memory region of the end address for a screen display from an addressand memory region information at a trigger position that is outputtedfrom the address generator 56 and the memory controller 58 to theuniversal register controller 60 and transfers an interrupt requestsignal that represents a data transmission of a display correspondingmemory region to the interrupt controller 62. The clock controller 66receives clock signals from the PCI bus, the external clock generator,the target, and so on to generate internal and external clock signals ofthe interface means 32. Also, the clock controller 66 has a built-inphase-locked loop (PLL) circuit for generating a high-speed samplingclock signal, which is used in a clock divider circuit and a logicanalyzer. The read-back/JTAG controller 68 reads values for internalnodes or registers of the FPGA and the MCU that constitute the target 34and other elements supporting a read-back/JTAG. JTAG is based on IEEE1149.1. The read-back/JTAG controller 68 receives informations such as auser-set location information of the internal nodes or registers of theelements in which a read-back/JTAG will be performed, and the number ofa clock step to perform a continuous operation and then controls ageneration of and a storage of a read-back/JTAG input and output signalsof the corresponding elements based on the informations. Theparallel/serial converter 70 converts a serial data to a parallel dataor a parallel data to a serial data. The data compression/restorationcontroller 72 performs a restoration operation when compressed datastored in the memory 40 of the interface means 32 are applied to thetarget 34 and performs a compression operation when normal data from thetarget 34 are applied to the interface means 32. The target interfacecontroller 74 controls an interface for data input and output operationsof the target 34. The bus termination circuit controller 76 receives aresult of a pin to signal allocation of the chip design verifying andchip testing program to perform a control as to whether the target 34 isconnected to the controller 42 or not, and makes the bus terminationcircuit 44 not to transmit data between the third connector C3 and thebus termination circuit 44. The glitch detector 78 detects a glitchelement contained in data from the target 34 and stores the clock numberat a position where the glitch element is detected or an address of thememory 40 of the interface means 32 in a separate register or the memory40 in order to display a location of the glitch element on a screen.

[0055] The interface means 32 described above performs both a signalapplication to the target 34 and a storage of a signal applied from thetarget 34. However, the interface means 32 may be used to perform onlyone of the two functions.

[0056] It can be set what usage of the interface means 32 has by usingthe graphic user interface displayed by performing the chip designverifying and chip testing program. For example, when three interfacemeans 32 are inserted into the PCI slots 24, a use of the interfacemeans 32 is set in such a way that the first interface means is used fora signal application (or pattern generator), the second interface meansis used for a signal storage (or logic analyzer), and the thirdinterface means is used for a signal application and storage (or apattern generator and a logic analyzer). An identification number isprovided to each of a plurality of the interface means by manipulatingthe DIP switch SW of the interface means 32, and a usage of a pluralityof the interface means 32 can, respectively, be set on the graphic userinterface using this identification number.

[0057] When the controller 42 of the interface means 32 of FIG. 4 isconfigured in FPGA and the interface means 32 is to be used for a partof the target 34, some blocks of the target as shown in FIGS. 3a and 3 bcan be configured in FPGA of the interface means 32. So, the interfacemeans 32 may be used as a target. That is, by configuring the controller42 in FPGA, when the interface means 32 is used as a target, someconfigurable blocks of FIGS. 3a and 3 b may be configured in the FPGA,and the memory blocks may be implemented using the memory 40 of theinterface means 32 having a relatively large capacity.

[0058]FIG. 6a shows an embodiment of a module for a connection betweenthe interface means and the target. As shown in FIG. 6a, the computermainframe 2 includes a mainframe case 6. A front surface of themainframe case 6 includes a portion 82 where the CD ROM drive and thehard disk drive are mounted and a portion 84 where a floppy disk driveis mounted. A back surface of the mainframe 6 includes slot ports 80. Amain board 4 is arranged in the mainframe 2 and includes a CPU slot 92,memory slots 90, the PCI slots 24, and the ISA slots 24.

[0059] The module 94 is mounted on the location 82 where a CD ROM driveand the hard disk drive of the mainframe 2 are mounted. The module 94includes a housing HG1, a board BD1, module connectors CB1 to CB4, areset switch RSW, and an LED indicator LED.

[0060] The third and fourth connectors C3 and C4 of the interface means32 of FIG. 4 are connected with the first and second module connectorsCB1 and CB2 of the module 94, respectively, through, for example, acable (not shown). The first module connector CB 1 of the module 94 isconnected with the third module connector CB3 through signal lines onthe board BD1, and the third module connector CB3 of the module 94 isconnected with the target 34 through, for example, a cable (not shown).The reset switch SW is connected with the second module connector CB2through signal lines on the board BD1. The LED indicator LED is anindicator that indicates a state of the module 94. The mainframe 2 canbe easily connected with the target 34 through the module 94 of FIG. 6a.

[0061]FIG. 6b shows another embodiment of a module for a connectionbetween the mainframe and the target. As shown in FIG. 6b, the module 96is mounted on a portion 82 where the CD ROM drive and the hard diskdrive are mounted. Even though the module 96 of FIG. 6b is mounted on aspace where two CD ROM drives are mounted, it may be mounted on a spacewhere three or four CD ROM drives are mounted.

[0062] The module 96 includes a housing HG2, upper and lower boards BD2and BD3, a back board BD4, upper and lower guides GD1 and GD2,respectively, mounted on inner surfaces of the upper and lower boardsBD2 and BD 3 and apposite to each other, fifth module connectors CB5arranged on an inner surface of the back board BD4, and sixth moduleconnectors CB6 arranged on an outer surface of the back board BD4. Thefifth and sixth module connectors CB5 and CB6 are connected with eachother through a signal line of the back board BD4.

[0063] The module 96 of FIG. 6b is configured to be able to accept atleast seven interfaces means, and thus since it can accept moreinterface means than the module 94 of FIG. 6A does, it can be applied tothe target 34 having a large number of input/output terminals.

[0064] However, when the interface means 32 are mounted on the module 96as shown in FIG. 6b, it is preferable that a connecting board is addedto connect the interface means 32 to the PCI slots 24 of the main board4.

[0065]FIG. 6c shows an embodiment of the connecting board that ismounted on the PCI slots 24 when the interface means is mounted on themodule of FIG. 6b. As shown in FIG. 6c, the connecting board PCB1includes seventh and eighth connectors CB7 and CB8. On the connectingboard PCB 1, signal lines for a connection between an inserting portionP1 and the seventh connector CB7 and signal lines for a connectionbetween the seventh and eighth connectors CB7 and CB8 are arranged. Atthis point, the inserting portion P1 of the connecting board of FIG. 6cis inserted into one of the PCI slots for a connection with the seventhconnector CB7.

[0066] The seventh connector CB7 is connected with the sixth connectorCB6 of the module 96 via, for example, a cable (not shown). The eighthconnector CB8 is used to connect external signals and corresponds to thefifth connector C5 of FIG. 4.

[0067] The module 96 of FIG. 6b may be configured in such a way thatonly one sixth connector CB6 mounted on the outer surface of the backboard BD4 is connected with the seventh connector CB7 of FIG. 6c, andthe connecting board PCB1 of FIG. 6c is mounted into one of the PCIslots. In this case, the fifth connectors CB5 are commonly connectedwith the sixth connector CB6 via signal lines of the back board BD4.

[0068]FIG. 6d shows an embodiment of an appearance form of the interfacemeans that is mounted on the module of FIG. 6b. As shown in FIG. 6d, aboard PCB2, ninth and tenth connectors CB9 and CB10, and a plate P2 areprovided. Components on the board PCB2 and signal lines are not shown inFIG. 6d.

[0069] The interface means 32 is configured on the board PCB2 of FIG.6d, and the ninth connector CB9 is connected with the fifth connectorCB5 of FIG. 6b. For example, the ninth connector CB9 is inserted intothe fifth connector CB5 of FIG. 6b. Even though the ninth connector CB9is connected with the fifth connector CB5 in FIG. 6d, the interfacemeans 32 may be configured in such a way that the fifth connector CB5 isformed in the form of a slot, and an inserting portion of the board PCB2is inserted into the slot-shaped fifth connector CB5. In this case, theninth connector CB9 is removed from the board CB9.

[0070]FIG. 6e shows another embodiment of the module for a connectionbetween the interface means and the target. Like that of FIG. 6b, amodule 98 of FIG. 6e is mounted on a portion 82 where the CD ROM driveor the hard disk drive are mounted. The module 98 includes a housingHG3, upper and lower boards BD5 and BD6, and a back board BD7. Upper andlower guides GD3-1, GD3-2, GD4-1, and GD4-2 are, respectively, mountedon the upper and lower boards BD5 and BD6 to be apposite to each other.Connectors CB5 are arranged on an inner surface of the back board BD7. Aconnector CB6 is arranged on an outer surface of the back board BD7.

[0071] The interface means 32 mounted between the upper and lower guidesGD3-1 and GD4-1 is firmly fixed by a fixing member F1. The fixing memberF1 is held by a fixing member holders FS1 and FS2. A target supporter F2supports the target 34 when the target 34 is attached to the connectionboard mounted between the upper and lower guides GD3-2 and GD4-2 for atarget debugging. In other words, the target supporter F2 is pulled outin order to support the target 34. The target supporter F2 is guided andheld by target supporting guides FS3 and FS4.

[0072] The upper and lower guides GD3-1, GD3-2, GD4-1, and GD4-2 may befixed directly to upper and lower portions of the housing HG3,respectively, not via the upper and lower boards BD5 and BD6. Theconnectors CB5 and CB6 are connected with each other via signal lines ofthe back board BD7.

[0073] The interface means 32 is mounted through the upper and lowerguides GD3-1 and GD4-1, and a target board or a connecting board for aconnection between the interface means 32 and the target 34 is mountedthrough the upper and lower guides GD3-2 and GD4-2. The fixing member F1is made of an elastic material such as a wire and serves to fix theinterface means 32 when the interface means 32 is mounted through theupper and lower guides GD3-1 and GD4-1. The fixing member F1 has asufficient width to be inserted into a space between the lower guidesGD4-1 and GD4-2. That is, it is preferable that the fixing member F1 hasa width equal to or slightly less than a gap between the lower guidesGD4-1 and GD4-2.

[0074] The interface means 32 is mounted by throwing down an externalconnecting lever of the fixing means F1 after the fixing member F1 islocated over a lever holder H. After mounting the interface means 32,when one's hand throwing down the external connecting lever F1-L of thefixing member F1 is taken off, the fixing member F1 moves toward a topportion of the lever holder H. Therefore, even when the target board ora connecting board for a connection between the interface means 32 andthe target 34 is attached or removed, the interface means 32 does notmove any more and is firmly fixed due to the fixing member F1. When anerror occurs in the target 34 after a verification for the target 34 isperformed, a debugging should be performed by verifying any nodes of thetarget 34. At this time, since a debugging can not be performed when thetarget 34 is mounted inside the module 98, the target 34 is taken outthe module 98 for an easy debugging. That is, after pulling the targetsupporter F2 outwardly, the connecting board for a connection betweenthe interface means 32 and the target 34 is mounted through the upperand lower guides GD3-2 and GD4-2, and the target board is connected withthe connecting board.

[0075] By the method described above, the interface means 32 can beeasily connected with the target 34 without opening the mainframe case.

[0076]FIG. 6f is an embodiment of the back board of the module accordingto the preferred embodiment of the present invention. The connectors CB5are arranged on an inner surface of the back board BD7. The connectorCB6 is located on an outer surface of the back board BD7. The back boardBD7 further includes a power switch PSW.

[0077] The connectors CB5 and CB6 are connected with each other viasignal lines SL, a control signal line CSL and power lines PL. Thesignal lines SL include the PCI signal line 48 of FIG. 4, signal linesof the first connectors C1 for a memory expansion, signal lines of thesecond connectors C2 for a connection of a plurality of the interfacemeans 32, and signal lines connected with an external portion through aback portion of the PCI. A connector CB11 serves to supply a main powersource, for example, for a personal computer, and a connector CB12serves to supply an auxiliary power source that is used to test a chip.The power switch PSW serves to cut off the main power source that isapplied from the connector CB11 under a control of the interface means32 when data are transmitted between the interface means 32 and thetarget 34 during a test operation. The main power source includes noiseelements such as a ripple noise and a ground noise and thus is notsuitable for the power source used to test a chip. Therefore, it ispreferable that the auxiliary power source is separated from the mainthe power source. When the interface means 32 is used as the patterngenerator and/or the logic analyzer, the main the power source suppliedvia the connector CB11 is used till data are transferred between themain memory 18 and the memory 40 of the interface means 32. However,after a data storage from the main memory 18 to the memory of theinterface means 32 is completed, the interface means 32 generates acontrol signal to the control signal line CSL to turn off the powerswitch PSW to cut-off the main power source, whereupon only a stableauxiliary power source is supplied to the power lines PL via theconnector CB12. When a data transmission between the interface means 32and the target 34 is completed, the interface means 32 generates acontrol signal to the control signal line CSL to turn on the powerswitch PSW, whereupon the main power source is supplied to the powerlines PL via the connector CB11. Due to the back board BD7 having such aconfiguration, since only the auxiliary power source is supplied duringa test operation, a stable test operation can be performed.

[0078]FIGS. 7a to 7 c shows a flow chart illustrating an internaloperation of the mainframe when the chip design verifying and chiptesting program of the chip design verifying and chip testing apparatusis executed. First, when the chip design verifying and chip testingprogram is executed, the CPU 10 brings an application program stored inthe hard disk 22 to a region of the memory 18 of FIG. 8 corresponding tothe chip design verifying and chip testing program, and displays the GUIof FIG. 9 on the monitor through the graphic signal processor 12 (step100).

[0079] A device user designates an initial value set for various kindsof variables, user-designated variables, and relevant variables usingthe GUI menu items (step 110). In the step 110, signals are allocated topins of the third and fourth connectors C3 and C4 of the interface means32 of FIG. 4. A size of each of the frame buffers of the interface means32 is determined, and a size of the chunk memory for a display operationis determined. An input data file to be inputted to the target or a fileof the hard disk 22 storing a test vector is designated, and a file ofthe hard disk 22 to store a data outputted from the target is alsodesignated. Further, an on-line or off-line mode is designated. In theon-line mode, data transmitted from the target 34 to the interface means32 are displayed on the monitor 1. In the off-line mode, datatransmitted from the target 34 to the interface means 32 are notdisplayed on the monitor but stored in a designated file of the harddisk 22. However, when both the on-line and off-line mode are designatedat the same time, data transferred from the target 34 to the interfacemeans 32 can be displayed on the monitor 1, stored in the designatedfile of the hard disk 22.

[0080] Then, the device user sets an operation mode of the interfacemeans 32 using menu items of the GUI (step 120). The operation modeincludes a verifying mode and a testing mode. In the verifying mode, itis set what usage of the interface means 32 has (i.e., a signalapplication or/and a signal storage), and an operation is performed thatapplies or/and stores the designated input and output files or the testvector file to/from the target continuously. In the test mode, it is setwhether to use the interface means 32 as a pattern generator or/and alogic analyzer, and an operation is performed that inputs or outputsdata of one frame unit to the target 34 at a high speed.

[0081] An initialization operation is performed according to aninitialization value set by the menu items of the GUI (step 130). In thestep 130, an initialization value is transferred to the interface means32 to perform an initialization operation.

[0082] The internal register values of the universal register controller60 are set according to the initialization values set by the menu itemsof the GUI and the operation mode (step 140). The internal registers ofthe universal register controller 60 store an identification number setby the switch SW of the interface means 32, informations regardingwhether to occupy the PCI bus, a signal transmission direction betweenthe main memory 18 and the interface means 32, a memory to be accessed,an interrupt for a transmission, an interrupt for a transmissiontermination, a speed monitoring value, a change of a frame size, aninformation regarding the last frame transmission, a reset information,etc.

[0083] The interface means 32 generates an interrupt signal to the CUP10 via the PCI bus (step 150).

[0084] The CPU 10 discriminates whether an interrupt signal from theinterface means 32 is reached (step 160). If an interrupt signal is notgenerated, the CPU 10 continuously looks out whether an interrupt signalis generated. On the other hands, when an interrupt signal is generated,the CPU 10 reads the internal register values of the universal registercontroller 60 and stores them in the universal register region of themain memory 18 of FIG. 8 (step 170).

[0085] The CPU 10 checks items to perform an operation according tovalues set in the universal register region of the main memory 18 (step180).

[0086] The CPU 10 sends the interface means 32 an acknowledge signalindicating that values in the universal register region are already read(step 190).

[0087] The CPU 10 discriminates whether values set in the universalregister region of the main memory 18 are set from the main memory 18 tothe interface means 32 (step 200).

[0088] If values set in the universal register region of the main memory18 are set from the main memory 18 to the interface means 32 in the step200, the interface means 32 transfers data stored in the frame bufferregion of the main memory 18 to one of the memories M1 to M4 of thememory 40 of the designated interface means 32 to which values set inthe universal register region of the main memory 18 designate (step210).

[0089] If values set in the universal register region of the main memory18 are not set from the main memory 18 to the interface means 32 in thestep 200, the interface means 32 transmits data stored in one of thememories M1 to M4 of the memory 40 of the designated interface means 32to which values set in the universal register region of the main memory18 designate to the frame buffer region of the main memory 18 (step220).

[0090] As a transmission of a first frame is completed, the internalregister values of the universal register controller 60 of thecontroller 42 of the interface means 32 are updated (step 230).

[0091] The CPU 10 moves a content of the frame buffer region of the mainmemory 18 to the chunk memory region of the main memory 18 to displaythe content of the frame buffer region on a window (step 240).

[0092] The contents in the chunk memory of the main memory 18 are sentto the graphic signal processor 12 to display them on a window (step250).

[0093] The CPU 10 discriminates whether the last frame is set in theuniversal register region of the main memory 18 and in the universalstate register 60 of the controller 60 of the interface means 32 (step260).

[0094] If the last frame is set in the universal register region of themain memory 18 and in the universal state register 60 of the controller60 of the interface means 32, an operation is finished. However, if thelast frame is not set in the universal register region of the mainmemory 18 and in the universal state register 60 of the controller 60 ofthe interface means 32, an operation turns to the step 150.

[0095]FIG. 8 shows an allocation of the memory region inside themainframe 2 when the chip design verifying and chip testing program isexecuted. The main memory 18 includes a chip design verifying and chiptesting program region, a frame buffer region, a chunk memory region,and a universal register region.

[0096]FIG. 9 shows an embodiment of the GUI displayed on the monitor ofFIG. 1 when the chip design verifying and chip testing program isexecuted. The GUI includes menu items required to perform a chip designverification and test and provides various window environments. The GUIenvironment of FIG. 9 provides only a waveform window that is widelyused for a general purpose, and a distribution window. However, the GUIenvironment of the present invention provides a waveform window for anaudio block, an image display window for a video block, a spectrumanalyzing window for a telecommunication block, a microprocessordevelopment system (MDS) environment for a MCU block, a windowindicating an arrangement on a two or three dimensional coordinates foran operation related to analysis between bus signals, a windowindicating a state of the periphery measuring instruments (e.g., anoutput voltage, an offset voltage, an output frequency, a duty ratio,etc), a window indicating a waveform generation, an environment of alogic analyzer used generally during an operation analysis of a digitallogic and a debugging. In other words, the GUI environment of thepresent invention provides not only a window environment suitable forfinding errors of each of the blocks that constitute the target 34 butalso a window environment capable of controlling both an external powersupply used for a verification and a frequency generator on a singlemonitor.

[0097] Since the chip design verifying and chip testing apparatus can beused a chip tester as well as a chip design verifier, the interfacemeans 32 should be able to be operated as the pattern generator and thelogic analyzer. In order to use the interface means 32 as the chiptester, the test vector should be already stored in the memory 40 of theinterface means 32. In case that a capacity of the test vector isrelatively small, no problem occurs. However, as a capacity of the testvector becomes larger, a capacity of the interface means 32 shouldbecome larger. As described above, a memory capacity of the interfacemeans 32 can be expanded. However, there is a limitation to expanding amemory capacity of the interface means 32, and thus it is preferable touse a method of compressing and then storing data in the interface means32. In other words, the test vector stored in the hard disk 22 iscompressed using a software program and then stored in the frame bufferregion of the main memory 18, and the compressed data are stored in thememory 40 of the interface means 32. The interface means 32 restores thecompressed data by the data compression/restoration controller 72 of thecontroller 42 and then transmits them to the target 34.

[0098] On the other hands, data inputted from the target 34 arecompressed by the data compression/restoration controller 72 of thecontroller 42 of the interface means 32 and then stored in the memory40. The compressed data are stored in the frame buffer region of themain memory 18, and the compressed data stored in the frame bufferregion are restored using a software program to be displayed on the GUI.

[0099] A compression and restoration method according to the preferredembodiment of the present invention is explained below with reference todrawings.

[0100]FIG. 10 is a table showing a meaning of a symbol with respect to asymbol code. The symbol code represents a data logic state andconstitutes the test vector. In the table of FIG. 10, a symbol “0”denotes a code “000” and means an input low, a symbol “1” denotes a code“001” and means an input high. A symbol “L” denotes a code “010” andmeans an output low, and a symbol “H” denotes a code “011” and means anoutput high. A symbol “S” denotes a code “100” and means a week low, anda symbol “T” denotes a code “101” and means a week high. A symbol “Z”denotes a code “110” and means a high impedance, and a symbol “X”denotes a code “111” and means an unknown. The test vector of the sameform as shown in FIG. 10 is stored in the hard disk 22 of the mainframe2.

[0101]FIG. 11 shows a data format when an input file selected by thechip design verifying and chip testing program is compressed using asoftware program and then is transmitted. The data format includes aflag of one bit, a run length of three or four bits, a code, and run.

[0102] In the flag, when a logic state comes under either no statevariation or a state variation of the highest frequency already defined,“0” is inscribed. If not so, “1” is inscribed. At this point, a logicstate that comes under a state variation of the highest frequencyalready defined represents cases that a logic state varies from “0” to“1”, form “1” to “0”, from “L” to “H”, and from “H” to “L” in the tableof FIG. 10.

[0103] The run length is a value that determines a length of a runarranged at the end portion of the data format. When the input andoutput signals that constitutes the test vector is more than 128 innumber, four bits are allocated in the run length, whereas when theinput and output signals that constitutes the test vector is less than128 (i.e., 0 to 127) in number, three bits are allocated in the runlength.

[0104] A code is one that indicates a symbol of logic state of FIG. 10,and a length of the code is determined by the flag. When the flag is“0”, a length of the code is one bit. At this point, a code “0” meansthat there is no a state variation, and a code “1” means that there is astate variation. When the flag is “1”, a length of the code is threebits, and one of eight codes of FIG. 10 is inscribed.

[0105] In the run, the number of times that the designated logic stateis repeated is inscribed.

[0106] In general, input data include eight logic states of FIG. 10 andare stored in a recording medium such as the hard disk 22 of themainframe 2. When an input file is selected to perform a verification ora test, data are compressed by a software program and then stored in theframe buffer region of the main memory 18. Then, the compressed datastored in the frame buffer region are stored in the memory 40 of theinterface means 32.

[0107] A method of compressing data by a software program using the chipdesign verifying and chip testing program is explained with reference toFIGS. 12 and 13.

[0108]FIG. 12 shows an embodiment of the test vector stored in the harddisk. Twenty data of from “A” to “T” represent a logic state of eachsignal according to a time variation and are compressed in the same formas shown in FIG. 13 and is transferred in the data format of FIG. 11.FIG. 13 shows input and output data of the test vector that arecompressed in the data format of FIG. 11, and a logic state of and a runof the input data of FIG. 12.

[0109] As shown in FIG. 13, the logic state and the run of a first rowdata of the input data of FIG. 12 can be represented asH(5)L(2)0(3)1(2)0(1)1(5)X(2). H(5) is coded as “1_(—)011_(—)011_(—)101”,and L(2) is coded as “1_(—)010_(—)010_(—)10”, and 0(3) is coded as“1_(—)010_(—)000_(—)11”. After the input data are coded in the same formas the first compressed input data of FIG. 13, the input data aretransmitted. The logic state and the run of a second row data of FIG. 13can be represented as o(2)0(2)1(3)o(8)0(1)o(4), which represents avariation of from the first row data to the second row data. At thispoint, “o” means a case that the flag is “0”, a code is “0”, andtherefore there is no variation of the logic state; “0” means a casethat the flag is “0”, a code is “1”, and therefore there is a variationof the logic state; and “1” means a case that the flag is “1”, and acode has a value of one of eight logic state of FIG. 9.

[0110] Therefore, data A and B of the first and second row data of thetable of FIG. 12 are maintained from HH to HH and thus are representedas o(2). Data C and D of the first and second row data of the table ofFIG. 12 vary from HH to LL and thus are represented as 0(2). Using themethod described above, the logic state and the run of the second inputdata are represented as shown in FIG. 13. Also, when these data arechanged into the data format of FIG. 11, these data are represented asthe compressed input data of the table of FIG. 13. Using the methoddescribed above, the third and fourth row input data can also berepresented as the logic state, the run and the compressed input data ofthe table of FIG. 13.

[0111] When an input file stored in the hard disk 22 is selected usingthe menu items on the GUI by performing the chip design verifying andchip testing program, and data compression mode is designated, the inputdata constituting the test vector stored in the input file arecompressed by a software program through the data compression methoddescribed above and then are transmitted to the interface means 32.

[0112] A data restoration is performed by reversely performing thecompression method described above, and thus its explanation is omitted.

[0113] The data compression method is one which compresses all of theinput data and the output data into one file without dividing the inputdata and the output data of the test vector. However, in the step 110 ofFIG. 7, in a state that the input data and the output data transmittedthrough the third connector C3 are designated to correspond torespective pins, the compressed test vector can be divided into theinput data and the output data to be processed as separate files.

[0114] A method of verifying an abnormal operation of the target for theformer compression method is as follows. First, the datacompression/restoration controller 72 of the controller 42 of theinterface means 32 restores data stored in the memory 40 by a hardware,e.g., a restoration circuit, by the data restoration method. Then, thedata compression/restoration controller 72 applies the input data to thetarget 34. Also, the data compression/restoration controller 72 comparesthe output data with data outputted from target 34 via the triggercondition controller 64 to store an address where the comparison resultis a mismatch in the memory. A mismatch is continuously counted to bestored in the memory. When a corresponding address and a mismatchcounter, which represent a mismatch result, reach a user designatedcounter value, a comparison operation is not performed any more.

[0115] A method of verifying an abnormal operation of the target for thelater compression is as follows. First, the compressed input test vectorin the hard disk 22 is transmitted to the memory 40 of the interfacemeans 32 via the main memory 18, and the data compression/restorationcontroller 72 of the controller 42 of the interface means 32 restoresdata stored in the memory 40 by a hardware, e.g., a restoration circuit,by the data restoration method and then applies them to the target 34.Data outputted from the target 34 are compressed by a hardware, e.g., acompression circuit, by the data compression method described above andthen are stored in the memory 40. The compressed output data stored inthe memory 40 are transferred to the main memory 18 again. And thecompressed data in the main memory 18 are restored by the softwareprogram of the data compression/resotration and are compared with theoutput test vector already stored in the main memory 18.

[0116] As another embodiment of compressing the test vector, whencompressing data stored in the main memory 18 and transmitting them tothe interface means 32, data can be compressed using the datacompression/restoration controller 72 of the controller 42 of theinterface means 32 other than a software program. This method is amethod that stores the input data constituting the test vector stored inthe hard disk 22 in the memories M1 and M2 of the memory 40 of theinterface means 32, compresses the input data stored in the memories M1and M2 of the interface means 32 by the data compression/restorationcontroller 72 and then stores them in the memories M3 and M4, and storesdata stored in the memories M3 and M4 in the hard disk 22 through themain memory 18. At this moment, a connection with the target 34 isdisconnected.

[0117] In case that the input file of or the test vector file of thetarget 34 is already compressed and stored in the hard disk 33, anaccess time of the hard disk 22 to read and store files of the same sizecan be as reduced as a data compression ratio.

[0118] Since data are compressed and transmitted during a datatransmission between the main memory 18 and the interface means 32, thechip design verifying and chip testing apparatus can perform ahigh-speed data transmission. Further, since a large-sized test vectoris compressed and stored in the memory 40 of the interface means 32, alarge-sized test vector can be stored in the relatively small-sizedmemory 40. Therefore, it is possible to effectively use the main memory18 and the memory 40 of the interface means 32, which have a limitationto using the interface means 32 as the pattern generator and the logicanalyzer.

[0119]FIGS. 14a to 14 c are a flow chart illustrating a chip designverifying method by the inventive chip design verifying and chip testingapparatus and show a target matching process to enable the hardwaremodel of and the software model of the target to show the same result asthe simulation result by using the test vector having a regular timeinterval prepared by the simulation result, prior to performing averification of the target 34. In FIGS. 14a to 14 c, a method ofpreparing the compressed test vector is carried out according to thelater compression method.

[0120] First, the chip design verifying and chip testing program isexecuted, so that the GUI environment is displayed on the monitor 1(step 300).

[0121] Initial values set for various variables, user designatedvariables, and relevant variables are designated through the menu itemsof the GUI environment (step 310).

[0122] The operation mode is set to the verification mode through themenu items of the GUI environment (step 320). In other words, whether touse the interface means 32 to apply signals and/or to store signals isset.

[0123] The steps 300 through 320 are performed in the same method as thesteps 100 through 120 of FIG. 7.

[0124] The test vector file is designated through the GUI menu items(step 330). When the test vector file is selected, the vector file isdisplayed on a window.

[0125] A comparison starting location or a comparison starting conditionfor the vector file loaded on the window is designated through a windowenvironment (step 340). That is, a condition to perform a comparison, alocation of a certain signal to start a comparison, and a pattern to bematched are designated.

[0126] The test vector is applied to the target 34 through the memory 40of the interface means 32 in a frame unit, and data received from thetarget 34 through the memory 40 of the interface means 32 are comparedwith expected data (step 350).

[0127] The CPU 10 discriminates whether the inputted data are consistentwith the expected data (step 360).

[0128] When the input data are consistent with the expected data, it isdiscriminated that the last frame is received (step 370). When the lastframe is received, an operation is finished.

[0129] When the input data are no consistent with the expected data, theCPU 10 finds a starting location of a mismatch from the comparisonstarting location/condition to move to the starting location of amismatch. (step 380). That is, it moves to a corresponding location on awindow.

[0130] A condition to approach a neighboring location just before amismatch occurs is set as a trigger condition through the GUIenvironment (step 390). In this step, if the designed chip includes theMCU and the ROM and it is required to perform a debugging whilemonitoring a instruction command performing process, the same assemblycode produced the ROM code is loaded on the GUI environment, and abrake-point for an address of a portion having doubts is set. At thismoment, an address to be set as the brake-point is stored in the triggercondition controller 64 of the interface means 32.

[0131] The test vector is applied to the target 34 in a frame unitthrough the memory 40 of the interface means 32, and the triggercondition controller 64 of the interface means 32 compares the dataoutputted from the target 34 with the trigger condition (step 400).

[0132] The trigger condition controller 64 of the interface means 32discriminates whether the trigger condition is matched (step 410). Also,in the step 410, the trigger condition controller 64 of the interfacemeans 32 discriminates whether an address of the ROM to be applied fromthe target 34 to the interface means 32 is consistent with an addressset as the brake-point. When the trigger condition is matched, theinterface means 32 stop inputting the clock signals applied to thetarget 34 from the clock controller 66 (step 420). Alternately, when theaddress of the ROM to be applied from the target 34 to the interfacemeans 32 is consistent with the address set as the brake-point, an inputof the clock signals applied from the clock controller 64 of theinterface means 32 to the target 34 is stopped.

[0133] A designation of signals regarding the read-back/JTAG nodes,internal probing nodes and external probing nodes, which are requiredfor a debugging, is performed using the GUI (step 430).

[0134] A trigger condition for a location just before an error occurs isset using an I/O frame step number, a clock step number, input andoutput signals and/or signals of probing nodes through the GUI (step440).

[0135] In response to clock signals corresponding to a trigger conditionalready set, data outputted from the target 34 are displayed on themonitor (step 450). For example, if the clock step number is set to“five” in the GUI environment as a trigger condition, in response toclock signals of five times outputted from the clock controller 66 ofthe interface means 32 to the target 34, data outputted from the target34 are all stored in the memory 40 of the interface means 32, and thendata stored in the memory 40 are displayed on the GUI environment.

[0136] Then, it is discriminated whether it reaches an error location ornot (step 460). If not so, the steps 440 and 450 are repeatedlyperformed. If it reaches an error location, a cause of an error isanalyzed through a process that it reaches a mismatch location (step470).

[0137] It is discriminated whether a cause of an error is found (step480).

[0138] When a cause of an error is found, a hardware or a software modelof the target 34 is corrected (step 490). When a portion including acause of an error exists in the field programmable gate array that is ahardware model, a block including the cause of an error is corrected toproduce the bit stream for the field programmable gate array, so thatthe field programmable gate array is reprogrammed. Also, when a portionincluding a cause of an error exists in the ROM code that is a softwaremodel, the assembly code of the portion is corrected to update the ROMcode.

[0139] If a cause of an error is not found in the step 480, signalsregarding the read-back/JTAG nodes, internal probing nodes and externalprobing nodes are additionally designated, and then an operation turnsto the step 340 (step 500) FIGS. 15a to 15 c are flow chartsillustrating an operation to verify the target using the chip designverifying and chip testing apparatus according to the preferredembodiment of the present invention. A debugging is performed afterperforming the target matching process of FIG. 14 or after looking overan operation of the target through this process.

[0140] The steps 600 to 620 are the same as the steps 300 to 320 of FIG.14, and their explanation is omitted.

[0141] After performing the step 620, an input file inputted to inputpins of the target 34 and an output file outputted from output pins ofthe target 34 are designated (step 630) through the GUI.

[0142] Storage and display start condition of the output file aredesignated through the GUI (step 640).

[0143] The input file is applied in a frame unit through the interfacemeans 32 to the target 34, and an output of the target 34 is displayedon a window to verify an operation of each of components of the target34 according to various designated conditions(step 650).

[0144] It is discriminated whether the trigger condition is set andmatched (step 660).

[0145] When the trigger condition is not matched, it is discriminatedwhether an operation result of each component is satisfactory (step670).

[0146] Alternately, if an operation result of each component issatisfactory, it is discriminated whether the last frame is transferred(step 680). When the last frame is transferred, an operation isfinished, and when the last frame is not included, an operation turns tothe step 650.

[0147] Also, if the trigger condition is matched, an operation of thetarget 34 is stopped at a trigger location to display the triggerlocation on a window (step 700).

[0148] If an operation result of each component is not satisfactory, asoftware trigger condition is set at a location adjacent to an abnormaloperation on a window where an operation is not good or on a windowwhere it is discriminated that there is a mutual relation, or a hardwaretrigger condition is set by changing the operation mode of theneighboring interface board to the logic analyzer mode (step 690).

[0149] The steps 710 to 780 are the same as the steps 430 to 500, andthus their explanation is omitted. In the flow chart of FIGS. 14 and 15,an operation between the GUI environment and the interface means 32 isexplained in FIG. 7 and thus omitted. The chip design verifying and chiptesting apparatus receives or outputs data continuously during a datatransmission among the main memory 18, the interface means 32 and thetarget 34 in the verification mode.

[0150]FIGS. 16a to 16 c are views illustrating a data transmissionmethod among the main memory 18, the interface means 32 and the target34 of the inventive chip design verifying and chip testing apparatus,and particularly a data transmission method when the interface means 32is designated for signal application and storage.

[0151] Of four memories M1 to M4 of the interface means 32, two memoriesM1 and M2 are used to store data applied from the main memory 18 to theinterface means 32, and the rest two memories M3 and M4 are used tostore data from the target 34 to the interface means 32.

[0152] In the data transmission method of FIGS. 16a to 16 c, when a testvector stored in the hard disk 22 is selected through the GUI menu itemsand data compression items are designated, the test vector stored in thehard disk 22 is compressed by a software program to be stored in theframe buffer of the main memory 18. The compressed data stored in theframe buffer region of the main memory 18 are alternately stored in thememories M1 and M2 of the interface means 32.

[0153] When data are transmitted from interface means 32 to the target34, the compressed data stored in the memories M1 and M2 are alternatelyrestored and then transmitted by the data compression/restorationcontroller 72 of the controller 42 of the interface means 32. Also, whendata are transmitted from the target 34 to the interface means 32, thedata from the target 34 are compressed by the datacompression/restoration controller 72 of the controller 42 of theinterface means and then stored alternatively in the memories M3 and M4.The data stored in the memories M3 and M4 are alternately transferred tothe frame buffer region of the main memory 18, and compressed datastored in the frame buffer region are restored by a software program,e.g., a restoration program, and then stored in a chunk memory region ofthe main memory 18.

[0154]FIG. 16a shows a data transmission method when a data transmissionspeed of from the interface means 32 to the target 34 are equal to adata transmission speed of from the target 34 to the interface means 32.

[0155] In FIG. 16a, hatched data represent compressed data and includedata P2S transmitted from the main memory 18 to the interface means 32and data S2P transmitted from the interface means 32 to the main memory18. Non-hatched or dotted data denote restored data and include data S2Ttransmitted from the interface means 32 to the target 34 and data T2Stransmitted from the target 34 to the interface means 32. In the firstinterval {circle over (1)}, the compressed data transmitted from themain memory 18 to the interface means 32 are stored in the memory M1. Inthe second interval {circle over (2)}, the compressed data stored in thememory M1 of the interface means 32 are restored by the datacompression/restoration controller 72 of the controller 42 of theinterface means 32 and then transmitted to the target 34. At the sametime, data from the target 34 are transmitted to the interface means 32,and the compressed data transmitted from the main memory 18 to theinterface means 32 are stored in the memory M2. In the third interval{circle over (3)}, the compressed data stored in the memory M3 aretransmitted to the main memory 18, and compressed data stored in thememory M2 are restored by the data compression/restoration controller 72of the controller 40 of the interface means 32 and then transmitted tothe target 34, and at the same time, data from the target 34 aretransmitted to the interface means 32 so that the data are compressed bythe data compression/restoration controller 72 of the controller 40 ofthe interface means 32 and then are stored in the memory M4. After thecompressed data are transmitted from the interface means 32 to the mainmemory 18, the compressed data from the main memory 18 are transmittedto the memory M1 of the interface means 32. In the same method, in thefourth to sixth intervals {circle over (4)}, {circle over (5)} and{circle over (6)}, data are “continuously” transmitted from theinterface means 32 to the target 34 or from the target 34 to theinterface means 32.

[0156]FIG. 16b shows a data transmission method when a data transmissionspeed of from the target 34 to the interface means 32 is faster thanthat of from the interface means 32 to the target 34.

[0157] In FIG. 16b, in the first interval {circle over (1)}, thecompressed data transmitted from the main memory 18 to the interfacemeans 32 are stored in the memory M1. In the second interval {circleover (2)}, the compressed data stored in the memory M1 of the interfacemeans 32 are restored by the data compression/restoration controller 72of the controller 42 of the interface means 32 and then transmitted tothe target 34. At the same time, data from the target 34 are transmittedto the interface means 32. At this moment, data transmitted from thetarget 34 to the interface means 32 are compressed by the datacompression/restoration controller 72 of the controller and then storedin the memory M3. Compressed data transmitted from the main memory 18 tothe interface means 32 are stored in the memory M2. At the same timethat a storage operation in the memory M3 are completed, the compresseddata begins to be stored in the memory M4, and the compressed datastored in the memory M3 are transmitted to the main memory 18. At thismoment, data transmitted to the interface means 32 are compressed by thedata compression/restoration controller 72 and then stored in the memoryM4, and at the same time, data transmitted to the interface means 32 arecompressed by the data compression/restoration controller 72 and thenstored in the memory M3. At this moment, the compressed data stored inthe memory M4 are transmitted to the main memory 18. If the compresseddata in the memory M1 are restored by the data compression/restorationcontroller 72 and then transmitted completely while a storage operationin the memory M3 are performed, data in the memory M2 are restored bythe data compression/restoration controller 72 and begins to be appliedto the target 34, and the memory M1 stores the compressed datatransmitted from the main memory 18.

[0158] In the third and fourth intervals {circle over (3)} and {circleover (4)}, a data transmission is performed by the method describedabove.

[0159]FIG. 16c shows a data transmission method when a data transmissionspeed of from the target 34 to the interface means 32 is slower thanthat of from the interface means 32 to the target 34. Explanation ofFIGS. 16a and 16 b will help an understanding for FIG. 16c.

[0160] The interface means 32 can continuously transmit data even when adata transmission speed of from the interface means 32 to the target 34differs from that of from the target 34 to the interface means 32. InFIGS. 16a to 16 c, T1, T2 and T3 denote a speed margin. An operation isperformed by detecting a present address of a corresponding memory at atime when data are completely transmitted from the main memory 18 to theinterface means 32 or at a time when data are completely transmittedfrom the interface means 32 to the main memory 18, and an optimumoperable speed between the interface means 32 and the target 34 can beautomatically controlled by the CPU 10 monitoring the speed margins T1,T2 and T3. That is, an operation speed can be controlled in such a waythat the CPU 10 controls the clock controller 66 of the controller 42 inthe interface means 32.

[0161]FIGS. 17a and 17 b are a flow chart illustrating a chip testingmethod according to the preferred embodiment of the present inventionand shows that the target 34 includes the hardware and software modelsembodied in the same method as that of FIG. 14. An operation of thesteps 800 to 840 is equal to that of the steps 300 to 340 of FIG. 14.However, in the step 810, the frame buffer is designated to an initialvalue, according to a size of the test vector, a size of the framebuffer region of the main memory 18 and a size of the frame bufferregion of the memory 40 of the interface means 32. When a size of thememory 40 of the interface means 32 is relatively small, either a memoryboard having the same memories as the memories M1 to M4 of the memory 40of the interface means 32 or the memory 40 of the neighboring interfacemeans 32 that is not being used may be connected to the first connectorC1. In the step 820, an operation mode of the interface means 32 is setto the pattern generator and/or the logic analyzer.

[0162] After storing all of the input data constituting the test vectorin the memory 40 of the interface means 32, data stored in the memory 40of the interface means 32 are applied to the target 34, and dataoutputted from the target 34 are compared with expected data (step 850).That is, in case of testing a chip, after storing all of the input dataconstituting test vector in the memory of the interface means 32, dataare transmitted between the interface means 32 and the target 34 at thesame speed of an operation speed of the chip that is a target.Therefore, a test can be performed even when an operation speed of thechip is high.

[0163] Then, it is discriminated whether a comparison result is matched(step 860). When a comparison result is matched, it is discriminatedwhether the test vector is the last one. When the test vector is thelast one, an operation is finished (step 870). However, when the testvector is not last one, an operation turns to the step 830. Also, whenthe comparison result is not matched, it is discriminated whether asampling location change is required or not (step 880).

[0164] When a sampling location change is required, a process to find afirst mismatch error after the comparison start location/condition isperformed (step 890)

[0165] A device user changes a sampling location for signals causing theproblem during a process to prepare the test vector to update the testvector and then an operation turns to the step 830 (step 900).

[0166] When a sampling location change is not required, tested chips isseparated as an error chip, and then an operation is finished (step910).

[0167] As described above, the chip design verifying and chip testingapparatus according to the preferred embodiment of the present inventionuses the interface means to apply and store signals to continuouslyinput the test vector file or the input data to the target through theinterface means and to continuously receive data from the target throughthe interface means. Also, during a chip test operation, the interfacemeans is set as the pattern generator and/or the logic analyzer, thetest vector file is stored in the interface means, and data can betransmitted between the interface means and the target at a high speed.

[0168] As described herein before, the inventive chip design verifyingand chip testing apparatus has the following advantages. Firstly, theinventive chip design verifying and chip testing apparatus can be usedboth as a chip design verifier to verify an operation of the designedchip and to debug an error, based on a computer system and as a chiptester to test an operation of the manufactured chip. Secondly, sincedata to be stored the memory of the interface means are compressed andtransmitted, a data transmission speed and an apparatus performance canbe improved. Thirdly, since the inventive chip design verifying and chiptesting apparatus uses the GUI environment to display windows suitablefor finding errors of blocks constituting a designed chip or amanufactured chip, error of corresponding blocks can be easily founded.Fourthly, since the inventive chip design verifying and chip testingapparatus can be constituted in a manner that an application program isinstalled in a computer, and the interface board is mounted in the PCIslots, the inventive chip design verifying and chip testing apparatuscan be easily embodied. Fifthly, since the inventive chip designverifying and chip testing apparatus can set the interface means as alogic analyzer during an error debugging and display data outputted froma chip on a monitor according to the clock step number, a more precisedebugging can be performed.

[0169] While the invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

What is claimed is:
 1. A chip design verifying and chip testingapparatus, comprising: a storing means for storing an applicationprogram verifying an operation of a designed chip and testing amanufactured chip having a plurality of blocks, an I/O file, and a testvector; an interface means controlling a data transmission between thestoring means and the chip, and having a data applying means forapplying the I/O file and/or the test vector outputted from the storingmeans and a data storing means for storing data outputted from the chip;and a computer including a CPU for performing and controlling theapplication program.
 2. The apparatus of claim 1, wherein when theapplication program is executed, a graphic user interface is displayedon a monitor of the computer, and a verifying mode or a testing mode isset through the graphic user interface, and result data obtained byperforming the mode set are displayed through corresponding windowscorresponding to each of the plurality of the blocks.
 3. The apparatusof claim 2, wherein the interface means includes a plurality ofinterface blocks, and each of the plurality of the interface blocks isdesignated as the data applying means, the data storing means, or thedata applying and storing means using the graphic user interface.
 4. Theapparatus of claim 1, wherein a condition for a portion of the I/O fileand/or the test vector to be compared is designated using the garphicuser interface.
 5. The apparatus of claim 1, wherein the interface meansincludes a controller for controlling a data transmission between thestoring means and the data applying means, between the data applyingmeans and the chip, between the chip and the data storing means, andbetween the data storing means and the sotring means.
 6. The appratus ofclaim 1, wherein the data applying means includes first and secondmemories for storing data consitituting the input file and/or the testvector stored in the storing means.
 7. The apparatus of claim 1, whereinthe data storing means includes third and fourth memories for storingdata outputted from the chip.
 8. The apparatus of claim 6, wherein thedata applying means alternately applies data stored in the first andsecond memories to the chip while dividing data constituting the inputfile and/or the test vector file stored in the storing means into apredetermined unit and alternately storing them in the first and secondmemories, in the verifying mode, and stores data constituting the testvector stored in the storing means in the first and second memories andthen applies data stored in the first and second memories to the chip inthe test mode.
 9. The apparatus of claim 7, wherein the data storingmeans alternately outputs data stored in the third and fourth memoriesto the graphic user interface while alternately storing data appliedfrom the chip in the third and fourth memories, in the verifying mode,and alternately outputs data stored in the third and fourth memories tothe graphic user interface after storing data applied from the chip inthe third and fourth memories, in the test mode.
 10. The apparatus ofclaim 2, wherein the application program compresses data constitutingthe input file and/or the test vector by a data compression/restorationprogram and stores compressed data in the data applying means, andrestores the compressed data outputted from the data storing means bythe data compression/restoration program and transmits restored data tothe graphic user interface.
 11. The apparatus of claim 5, wherein thecontroller includes a data compression/restoration means for restoringcompressed data stored in the data applying means and transmittingrestored data to the chip, and compressing data ouputted from the chipand storing compressed data in the data storing means.
 12. The apparatusof claim 11, wherein the application program stores data constitutingthe input file and/or the test vector in the data applying means, theinterface means compresses data stored in the data applying means by thedata compression/restoration means and stores compressed data in thedata storing means, and stores the compressed data stored in the datastoring means in the storing means.
 13. The apparatus of claim 5,wherein the controller enables a data transmission of from the dataapplying means to the chip and a data transmission of from the chip tothe data storing means to be continuously performed under a control ofthe CPU, in the verifying mode.
 14. The apparatus of claim 5, whereinthe controller controls an operation speed between the interface meansand the chip in such a way that the CPU monitors a data transmissionspeed between the storing means and the data applying means, between thedata applying means and the chip, between the chip and the data storingmeans, and between the data storing means and the storing means, in theverifying mode.
 15. The apparatus of claim 4, wherein when an erroroccurs in the chip in the verifying mode or in the test mode, anoperation of the chip is stopped; for an I/O frame step number, a clockstep number and/or an input and output of the chip corresponding to aneighboring location before a first mismatch or an error occurs, acondition corresponding to the neighboring location is set as a triggercondition through the graphic user interface; and while applying dataconstituting the input file and/or the test vector file to the chip andstoring data outputted from the chip, it is discriminated whether dataoutputted from the chip are consistent with the condition correspondingto the neighboring location, whereby the neighboring location before themismatch or the error occurs is traced for finding the cause of theerror.
 16. The apparatus of claim 15, wherein when a condition to reachthe neighboring location before the mismatch or the error occurs is setas a trigger condition using the graphic user interface in the verifyingmode or in the test mode, the data outputted from the chip are stored inthe data storing means in response to the clock number of the number oftimes corresponding to the set trigger condition and are displayed onthe graphic user interface until the trigger condition to find theneighboring location before the mismatch or the error occurs isconsistent with the data inputted to and/or outputted from the chip. 17.A chip design verifying and chip testing apparatus, comprising: astoring means storing an appliation program for verifying a designedchip and testing a manufactured chip having a plurality of blocks, anI/O file, and a test vector; a CPU performing and controlling theapplication program; a main memory for loading the application programstored in the storing means, the I/O file and/or the test vector; and acomputer including an interface means for controlling a datatransmission between the main memory and the chip, the interface meansincluding a data applying means for storing and applying the input fileand/or the test vector outputted from the storing means to the chip anda data storing means for storing data outputted from the chip; whereinwhen the application program is executed, the graphic user interface isdisplayed on a monitor of the computer, an operating mode of theinterface mean is set, the results obtained from performing an operationaccording to the operating mode are displayed on a corresponding window.18. The apparatus of claim 17, whwerein the interface means includes apredetermined number of interface blocks, and each of the predeterminednumber of the interface blocks is designated as the data applying means,the data storing means, or the data applying and storing means using thegraphic user interface.
 19. The apparatus of claim 17, wherein acondition for a portion of the input file and/or the test vector to becompared is designated using the garphic user interface.
 20. Theapparatus of claim 17, wherein the interface means includes a controllerfor controlling a data transmission between the main memory and the dataapplying means, between the data applying means and the chip, betweenthe chip and the data storing means, and between the data storing meansand the storing means.
 21. The apparatus of claim 17, wherein the dataapplying apparatus includes first and second memories storing dataapplied from the main memory.
 22. The apparatus of claim 17, wherein thedata storing means includes third and fourth memories storing dataoutputted from the chip.
 23. The apparatus of claim 21, wherein the dataapplying means alternately applies data stored in the first and secondmemories to the chip while dividing data constituting the input fileand/or the test vector file stored in the storing means by apredetermined unit size to alternately store the divided data in thefirst and second memories, in the verifying mode, and stores dataconstituting the test vector stored in the storing means in the firstand second memories and then applies data stored in the first and secondmemories to the chip in the test mode.
 24. The apparatus of claim 22,wherein the data storing means alternately outputs data stored in thethird and fourth memories to the graphic user interface whilealternately storing data applied from the chip in the third and fourthmemories, in the verifying mode, and alternately outputs data stored inthe third and fourth memories to the graphic user interface afterstoring data applied from the chip in the third and fourth memories, inthe test mode.
 25. The apparatus of claim 17, wherein the applicationprogram compresses data constituting the input file and/or the testvector by a data compression/restoration program and stores compresseddata in the data applying means, and restores the compressed dataoutputted from the data storing means by the datacompression/restoration program and transmits restored data to thegraphic user interface.
 26. The apparatus of claim 20, wherein thecontroller includes a data compression/restoration means for restoringcompressed data stored in the data applying means and transmittingrestored data to the chip, and compressing data ouputted from the chipand storing compressed data in the data storing means.
 27. The apparatusof claim 25, wherein the application program stores data constitutingthe input file and the test vector in the data applying means,compresses data stored in the data applying means by the datacompression/restoration means and stores compressed data in the datastoring means, and stores the compressed data stored in the data storingmeans in the storing means.
 28. The apparatus of claim 20, wherein thecontroller enables a data transmission of from the data applying meansto the chip and a data transmission of from the chip to the data storingmeans to be continuously performed under a control of the CPU, in theverifying mode.
 29. The apparatus of claim 20, wherein the controllercontrols an operation speed between the interface means and the chip insuch a way that the CPU monitors a data transmission speed between thestoring means and the data applying means, between the data applyingmeans and the chip, between the chip and the data storing means, andbetween the data storing means and the storing means, in the verifyingmode.
 30. The apparatus of claim 17, wherein when an error occurs in thechip in the verifying mode or in the test mode, an operation of the chipis stopped; for an I/O frame step number, a clock step number and/or aninput and output of the chip corresponding to a neighboring locationbefore a first mismatch or an error occurs, a condition corresponding tothe neighboring location is set as a trigger condition through thegraphic user interface; and while applying data constituting the inputfile and/or the test vector to the chip and storing data outputted fromthe chip, it is discriminated whether data outputted from the chip areconsistent with the condition corresponding to the neighboring location,whereby the neighboring location before the mismatch or the error occursis traced for finding the cause of the error.
 31. The apparatus of claim30, wherein when a condition to reach the neighboring location beforethe mismatch or the error occurs is set as a trigger condition using thegraphic user interface in the verifying mode or in the test mode, thedata outputted from the chip are stored in the data storing means inresponse to the clock number of the number of times corresponding to theset trigger condition and are displayed on the graphic user interfaceuntil the trigger condition to find the neighboring location before themismatch or the error occurs is consistent with the data inputted toand/or outputted from the chip.
 32. The apparatus of claim 18, whereineach of the predetermined number of the interface blocks is configuredin the form of a board and is inserted into slots in the computer. 33.The apparatus of claim 32, further comprising, a connection module forconnecting each of the predetermined number of the interface blocks withthe chip, wherein the connection module is mounted on a front surface ofa mainframe of the computer.
 34. The apparatus of claim 18, wherein thecomputer includes: a main board having a predetermined number of slots;a connection board being connected to the slots and having a firstconnector; and a connection module including a back board and a housing,the back board having a second connector connected to the firstconnector of the connection board and a predetermined number of thirdconnectors connected to the second connector, the housing having a firstguide for accepting the predetermined number of the interface blocksconnected to the predetermined number of the third connectors connectedto the back board and a second guide for accepting a predeterminednumber of connection blocks connected to the predetermined number of theinterface blocks.
 35. The apparatus of claim 34, wherein the back boardincludes: a computer power applying connector for applying an electricalpower for the computer to the interface blocks; a verification and testpower applying connector for applying an electrical power for averification and test to the interface blocks and the connection bolcksduring the verification and test; and a switching means for connectingthe computer power applying connector or the verification and test powerapplying connector in response to a control signal applied from theinterface means.
 36. A chip design verifying and chip testing method,comprising: providing a computer including a storing means, the storingmeans storing an application program for verifying a designed chip andtesting a manufactured chip having a plurality of blocks, an I/O file,and a test vector; executing the application program to display agraphic user interface on a monitor of the computer; storing alternatelydata constituting the I/O file and/or the test vector stored in thestoring means in a data applying means when an operating mode is set toa verification mode to verify an operation of the designed chip throughthe graphic user interface; storing alternately data outputted from thechip in the data storing means; storing alternately data constitutingthe I/O file and/or the test vector stored in the storing means in thedata applying means when an operating mode of the interface mean is setto a test mode to test the manufactured chip through the graphic userinterface; and storing data outputted from the chip in the data storingmeans while applying data constituting the input file and/or the testvector stored in the data applying means to the chip.
 37. The method ofclaim 36, further comprising, displaying the graphic user interface onthe monitor of the computer when the application program is executed;setting the verification mode or the test mode through the graphic userinterface; and performing the verification mode or the test mode todisplay corresponding results, respectively, to the plurality of blockson corresponding window.
 38. The apparatus of claim 37, wherein acondition for a portion of the I/O file and/or the test vector to becompared is designated using the garphic user interface.
 39. The metodof claim 37, further comprising, compressing and storing the input fileand/or the test vector in the data applying means, and restoring andapplying the data stored the data applying means when the input fileand/or the test vector stored in the storing means is applied to thechip; and compressing and storing data outputted from the chip in thedata storing means when data outputted from the chip are stored in thedata storing means.
 40. The method of claim 36, wherein a datatransmission of from the data applying means to the chip and a datatransmission of from the chip to the data storing means are continuouslyperformed.
 41. The method of claim 36, wherein an operation speedbetween the interface means and the chip is controlled by monitoring adata transmission speed between the storing means and the data applyingmeans, between the data applying means and the chip, between the chipand the data storing measn, and between the data storing means and thestoring means so that a data transmission may be continuously performed,in the verifying mode.
 42. The apparatus of claim 37, wherein when anerror occurs in the chip in the verifying mode or in the test mode, anoperation of the chip is stopped; for an I/O frame step number, a clockstep number and/or an input and output of the chip corresponding to aneighboring location before a first mismatch or an error occurs, acondition corresponding to the neighboring location is set as a triggercondition through the graphic user interface; and while applying dataconstituting the input file and/or the test vector file to the chip andstoring data outputted from the chip, it is discriminated whether dataoutputted from the chip are consistent with the condition correspondingto the neighboring location, whereby the neighboring location before themismatch or the error occurs is traced for finding the cause of theerror.
 43. The method of claim 42, wherein when a condition to reach theneighboring location before the mismatch or the error occurs is set as atrigger condition using the graphic user interface in the verifying modeor in the test mode, the data outputted from the chip are stored in thedata storing means in response to the clock number of the number oftimes corresponding to the set trigger condition and are displayed onthe graphic user interface until the trigger condition to find theneighboring location before the mismatch or the error occurs isconsistent with the data inputted to and/or outputted from the chip. 44.A chip design verifying apparatus, comprising: a storing means forstoring an application verifying an operation of a designed chip andtesting a manufactured chip having a plurality of blocks, and an 110file; an interface means controlling a data transmission between thestoring means and the chip, and having a data applying means for storingthe compressed data of the I/O file outputted from the storing means anda data storing means for storing the compressed data outputted from thechip; and a computer including a CPU for performing and controlling theapplication program.
 45. The apparatus of claim 44, wherein when theapplication program is executed, a graphic user interface is displayedon a monitor of the computer, and a verifying mode is set through thegraphic user interface, and results corresponding to the plurality ofthe blocks are displayed on a corresponding window.
 46. The apparatus ofclaim 45, wherein the interface means includes a plurality of interfaceblocks, and each of the plurality of the interface blocks is designatedas the data applying means, the data storing means, or the data applyingand storing means using the graphic user interface.
 47. The apparatus ofclaim 45, wherein a condition for a portion of the input file and/or thetest vector to be compared is designated using the garphic userinterface.
 48. The apparatus of claim 44, wherein the interface meansincludes a controller for controlling a data transmission between thestoring means and the data applying means, between the data applyingmeans and the chip, between the chip and the data storing means, andbetween the data storing means and the sotring means.
 49. The appratusof claim 45, wherein the data applying means includes first and secondmemories storing compressed data stored in the storing means.
 50. Theapparatus of claim 45, wherein the data storing means includes third andfourth memories storing compressed data outputted from the chip.
 51. Theapparatus of claim 49, wherein the data applying means restores andalternately applies data stored in the first and second memories to thechip while dividing and alternately storing a input file and/or a testvector applied from the storing means in a predetermined unit in thefirst and second memories.
 52. The apparatus of claim 50, wherein thedata storing means alternately outputs data stored in the third andfourth memories to the storing means while compressing and alternatelystoring data outputted from the chip.
 53. The apparatus of claim 45,wherein the application program compresses data constituting the inputfile and/or the test vector file by a data compression/restorationprogram when compressed data are stored in the data applying means, andrestores the compressed data stored in the storing means by the datacompression/restoration program when data stored in the data storingmeans are transmitted to the graphic user interface.
 54. The apparatusof claim 48, wherein the controller includes a datacompression/restoration means for restoring compressed data stored inthe data applying means and transmitting restored data to the chip, andcompressing data ouputted from the chip and storing compressed data inthe data storing means.
 55. The apparatus of claim 45, wherein thecontroller enables a data transmission of from the data applying meansto the chip and a data transmission of from the chip to the data storingmeans to be continuously performed under a control of the CPU.
 56. Theapparatus of claim 48, wherein the controller controls an operationspeed between the interface means and the chip in such a way that theCPU monitors a data transmission speed between the storing means and thedata applying means, between the data applying means and the chip,between the chip and the data storing measn, and between the datastoring means and the storing means, in the verifying mode.
 57. Theapparatus of claim 45, when an error occurs in the chip in the verifyingmode, an operation of the chip is stopped; for an I/O frame step number,a clock step number and/or an input and output of the chip correspondingto a neighboring location before a first mismatch or an error occurs, acondition corresponding to the neighboring location is set as a triggercondition through the graphic user interface; and while applying dataconstituting the input file and/or the test vector file to the chip andstoring data outputted from the chip, it is discriminated whether dataoutputted from the chip are consistent with the condition correspondingto the neighboring location, whereby the neighboring location before themismatch or the error occurs is traced for finding the cause of theerror.
 58. The method of claim 57, wherein when a condition to reach theneighboring location before the mismatch or the error occurs is set as atrigger condition using the graphic user interface in the verifyingmode, the data outputted from the chip are stored in the data storingmeans in response to the clock number of the number of timescorresponding to the set trigger condition and are displayed on thegraphic user interface until the trigger condition to find theneighboring location before the mismatch or the error occurs isconsistent with the data inputted to and/or outputted from the chip.